1. Field of the Invention
The present invention relates to a semiconductor device structure in which a vertical MOSFET using SiC is fabricated by ion implantation, and to a method of manufacturing the structure.
2. Description of the Related Art
Conventionally, to manufacture a vertical MOSFET that uses SiC by ion implantation, a mask for ion implantation of a source region has to be different in width from a mask for ion implantation of a base region (see JP 10-233503 A, for example).
Because of the use of different masks in ion implantation of a source region and a base region, the conventional semiconductor device manufacturing method described above increases the number of steps to manufacture the MOSFET. In addition, the process precision of each mask and the accuracy of aligning the two masks influence the channel length, which is one of the factors that determine characteristics of the MOSFET thus posing a great obstacle to device miniaturization. Furthermore, if device miniaturization is advanced, it brings another problem of increased JFET resistance, which is in a trade-off relation with channel resistance lowered by the miniaturization.